On Tue, Oct 05, 2010 at 02:39:00PM +0900, Jassi Brar wrote:
Yes we can have a kconfig entry for 'Controllable EPLL' but that seems orthogonal to ASoC because, for SMDKs, we choose to produce accurate signals hence need to manipulate EPLL. The only point is where to do it.
Well, there's two approaches the driver can take: one is to change the EPLL to deliver the clock rates which allow maximum flexibility, the other is to constrain the clock rates offered to applications based on the frequencies that can be generated from the current EPLL setup.
(our priority is accuracy of each IP's functioning rather than having all parts of SMDK playing nice with each other on such h/w design issues)
That'd be the problem, kind of - it does mean people can get burned when they pick up the BSP code and use it as a reference for their systems.
I hope you noticed that this clock hierarchy is a _very_ board specific thing. We can easily place SoCs' shared stuff in arch/arm/plat-samsung (or similar) Any suggestions, where do we place code shared by SMDK-boards ?
plat-samsung would probably be fine for that also - create a file called common-smdk or something. Some other things have gone for a plat-smdk style approach too, though I'm not sure how tasteful I find that personally.