1 Mar
2018
1 Mar
'18
8:40 p.m.
On Sat, Jan 27, 2018 at 09:50:25AM +0530, Guneshwor Singh wrote:
From: Sanyog Kale sanyog.r.kale@intel.com
In order to achieve better DMA performance and reduce download time for firmware and library, it is recommended to disable dynamic clock and power gating. In some scenarios, DMA may wait to accumulate more data and last chunk of data never gets completed if dynamic clock and power gating is kept enabled.
This doesn't apply against current code, please check and resend.