
29 Oct
2020
29 Oct
'20
5:52 p.m.
+static int wsa_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
+{
- struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
- u16 gain_reg;
- int offset_val = 0;
- int val = 0;
- switch (w->reg) {
- case CDC_WSA_RX0_RX_PATH_MIX_CTL:
gain_reg = CDC_WSA_RX0_RX_VOL_MIX_CTL;
break;
- case CDC_WSA_RX1_RX_PATH_MIX_CTL:
gain_reg = CDC_WSA_RX1_RX_VOL_MIX_CTL;
break;
- default:
return 0;
- }
- switch (event) {
- case SND_SOC_DAPM_POST_PMU:
val = snd_soc_component_read(component, gain_reg);
val += offset_val;
snd_soc_component_write(component, gain_reg, val);
missed from v1: offset_val is zero so the sequence is reading and writing the same thing. Is this intentional or useful?
break;
- case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component, w->reg,
CDC_WSA_RX_PATH_MIX_CLK_EN_MASK,
CDC_WSA_RX_PATH_MIX_CLK_DISABLE);
break;
- }
- return 0;
+}
[...]
+static bool wsa_macro_adie_lb(struct snd_soc_component *component,
int interp_idx)
+{
- u16 int_mux_cfg0 = 0, int_mux_cfg1 = 0;
these inits are ignored
- u8 int_mux_cfg0_val = 0, int_mux_cfg1_val = 0;
these as well
- u8 int_n_inp0 = 0, int_n_inp1 = 0, int_n_inp2 = 0;
and these are also ignored.
- int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8;
- int_mux_cfg1 = int_mux_cfg0 + 4;
- int_mux_cfg0_val = snd_soc_component_read(component, int_mux_cfg0);
- int_mux_cfg1_val = snd_soc_component_read(component, int_mux_cfg1);
- int_n_inp0 = int_mux_cfg0_val & 0x0F;
- if (int_n_inp0 == INTn_1_INP_SEL_DEC0 ||
int_n_inp0 == INTn_1_INP_SEL_DEC1)
return true;
- int_n_inp1 = int_mux_cfg0_val >> 4;
- if (int_n_inp1 == INTn_1_INP_SEL_DEC0 ||
int_n_inp1 == INTn_1_INP_SEL_DEC1)
return true;
- int_n_inp2 = int_mux_cfg1_val >> 4;
- if (int_n_inp2 == INTn_1_INP_SEL_DEC0 ||
int_n_inp2 == INTn_1_INP_SEL_DEC1)
return true;
- return false;
+}