The audio-graph-card driver has properties for configuring the clocking for DAIs within a component, but is missing properties for setting up the PLLs and sysclks of the component.
This patch adds the two new properties 'plls' and 'sysclks' so that the audio-graph-driver can fully configure the component clocking.
Signed-off-by: Richard Fitzgerald rf@opensource.cirrus.com --- .../bindings/sound/audio-graph.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/audio-graph.yaml b/Documentation/devicetree/bindings/sound/audio-graph.yaml index 4b46794e5153..9e0819205a17 100644 --- a/Documentation/devicetree/bindings/sound/audio-graph.yaml +++ b/Documentation/devicetree/bindings/sound/audio-graph.yaml @@ -39,6 +39,52 @@ properties: mic-det-gpio: maxItems: 1
+ plls: + description: | + A list of component pll settings. There are 4 cells per PLL setting: + - phandle to the node of the codec or cpu component, + - component PLL id, + - component clock source id, + - frequency (in Hz) of the PLL output clock. + The PLL id and clock source id are specific to the particular component + so see the relevant component driver for the ids. Typically the + clock source id indicates the pin the source clock is connected to. + The same phandle can appear in multiple entries so that several plls + can be set in the same component. + $ref: /schemas/types.yaml#/definitions/phandle-array + + plls-clocks: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + description: | + A list of clock names giving the source clock for each setting + in the plls property. + + sysclks: + description: | + A list of component sysclk settings. There are 4 cells per sysclk + setting: + - phandle to the node of the codec or cpu component, + - component sysclk id, + - component clock source id, + - direction of the clock: 0 if the clock is an input to the component, + 1 if it is an output. + The sysclk id and clock source id are specific to the particular + component so see the relevant component driver for the ids. Typically + the clock source id indicates the pin the source clock is connected to. + The same phandle can appear in multiple entries so that several sysclks + can be set in the same component. + $ref: /schemas/types.yaml#/definitions/phandle-array + + sysclks-clocks: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + description: | + A list of clock names giving the source clock for each setting + in the sysclks property. + +dependencies: + plls: [ plls-clocks ] + sysclks: [ sysclks-clocks ] + required: - dais