On 11/04/2015 06:58 PM, Nicolin Chen wrote:
On Wed, Nov 04, 2015 at 04:33:16PM +0100, Roberto Fichera wrote:
With the patch below I'm able to see the error happening. And more likely it happen just just afterwards the EVTERR notify the problem to the ISR. At this point the DMA simply stalls due to some problems, most likely because the SSI FIFO is in overflow or underflow condition. I will do add the code to dump the SSI
No, SSI FIFO under/overflow were caused by the DMA stall as their channels got error out -- SSI was still consuming the TX FIFO and filling the RX FIFO while DMA didn't move the data at all so SSI FIFOs got under/overflowed.
Yeah! The SSI is correctly reporting this problem because DMA is stalled for some reason.
I think that at this point we should in theory restart the DMA channel, but however how to fix this and why this is happening?
According to Reference Manual:
- The CHNERR[i] bit is set when a DMA request that triggers channel
i is received through the corresponding input pins and the EP[i] bit is already set;
- Externally triggered channel pending flag EP[i] is set by the
scheduler when the channel was activated by a DMA request. It can be cleared by the ith channel script.
It looks like your system made another DMA request while the SDMA was still in the middle of the transaction for the same channel.
I don't know because this is something I cannot control. I'm just setting up 2 cyclic dma for both TX and RX before to set both RDMAE and TDMAE and nothing else. The rest is done by the SDMA ISR.
I guess you should find a way to make less frequent DMA requests, making higher watermarks and larger burst size for example.
I can try to increase the FIFO watermark up to 15 elements, but after that I don't have more choices. The problem is that the TDM has to run continuously because the SLIC need it. I can eventually enable and disable the DMA requests depending by the active channels for optimization, but the problem still,why the DMA transfer is not triggered?