9 Sep
2019
9 Sep
'19
5:50 p.m.
On Mon, Sep 9, 2019 at 2:54 AM Mark Brown broonie@kernel.org wrote:
On Fri, Sep 06, 2019 at 12:46:24PM -0700, Curtis Malainey wrote:
From: Ben Zhang benzh@chromium.org
Instead of clearing RT5677_PWR_ANLG2 (MX-64h) to 0 at SND_SOC_BIAS_OFF, we only clear the RT5677_PWR_CORE bit which is set at SND_SOC_BIAS_PREPARE. MICBIAS control bits are left unchanged.
This is a bug fix so should have been at the start of the series rather than depending on the naming changes you had as patch 1.
Got it, will send bug fixes to the bottom of future series.