Re: [alsa-devel] (SoC) Does i.MX27's SSI work as I2S clock master?

On Sun, Nov 30, 2008 at 4:47 PM, ngc ngc@drvlabo.jp wrote:

Though I want to provide an oversampling clock with MCLK to the codec device, now the frequency of MCLK is same as SSI_CLK. Can't the MCLK provide the oversampling frequency?

I wrote the SSI driver for the MPC8610. It's the same circuitry, so I presume the same rules apply.

The main SSI clock must be 64 times the sample rate. This is because the SSI uses a clock pulse to send out one bit of sample. Each sample is normally 32 bits, of which only the most significant 24 have any real value. Since I2S is always stereo, 32 * 2 = 64 pulses per sample.

Does that answer your question?