On Sun, Apr 08, 2018 at 04:16:39AM +0200, Marek Vasut wrote:
Could you please provide a failed instance? It's been a while since I wrote the code. But I can tell that PM is supposed to be called by set_sysclk() only, while FP is used for bclk. If you clear PM when setting FP, the output of HCK could be messed.
Try feeding it the following values, The codec I use is PCM1808.
[1] fsl_esai_set_dai_sysclk[227] clk_id=0 freq=24576000 dir=1 [2] fsl_esai_divisor_cal[131] tx=0 ratio=2 usefp=0 fp=0 [3] fsl_esai_set_bclk[322] tx=0 freq=3072000 [4] fsl_esai_divisor_cal[131] tx=0 ratio=8 usefp=1 fp=8
So [1] tries to output HCKT (using FSYS) and to set its freq at 24MHz. If [2] is correct, you'd have HCKT outputting 24MHz.
Let's put this in the graph: FSYS (48MHz) --> PSR & PM (input_rate / 2) --> HCKT (24MHz)
[3] tries to output SCKT (bit clock) at 3MHz. So you got fp=8 and usefp=1. The combination of usefp=1 and fp=8 should bypass PSR/PM settings because both should be correctly configured:
HCKT (24MHz) --> FP (input_rate / 8) --> SCKT (3MHz)
If you set PM=0 at [4], the HCKT at [2] would be changed. So your change shouldn't be a good fix. Meanwhile, I don't see any problem of the driver at the FP/PM part. I think you can help me figure it out as it might because of something else. You may dump the PSR, PM here to check if HCKT is 24MHz.
Also, I think there is another bug in the fsl_esai_divisor_cal() now that I look at it.
If usefp = 0, then maxfp = 1 , then savesub = 0 and
I see. This actually would happen when PSR=0. And the ratio in this case is <= 256 (which could be satisfied by PM only). Btw, is this the reason why you got a "dirty" PM?
Anyway, this part is a bug. Would you like to fix it?
Thanks Nicolin