18 Aug
2013
18 Aug
'13
3:37 p.m.
On Fri, Aug 16, 2013 at 06:36:28PM +0100, Mike Dyer wrote:
Bit 9 of PLL2,3 and 4 is reserved as '0'. The 24bit fractional part should be split across each register in 8bit chunks.
Applied, thanks. Please remember to word wrap your commit messages within paragraphs.