On Thu, Feb 23, 2012 at 12:14 PM, Russell King - ARM Linux linux@arm.linux.org.uk wrote:
On Thu, Feb 23, 2012 at 11:04:59AM -0600, Timur Tabi wrote:
Russell King - ARM Linux wrote: We almost never use readl. I see that it is used in some places, but honestly I can't see how it can be valid. For instance, the mpic driver uses it in mpic_startup_ht_interrupt(). I don't understand how that's valid, since there's nothing preventing the readl() from happening *before* the writeb.
That just sounds broken. If readl() can happen before a writeb() issued in program order, how do most of the PCI drivers work?
I was under the impression that on powerpc io memory was mapped cache-inhibited and guarded, which provides most ordered, but not store to load ordering without an additional synchronization instruction. See http://cache.freescale.com/files/32bit/doc/app_note/AN3441.pdf on page 8.
PCI adds some additional complexity, since the PCI device is not connected directly to the CPU. One must consider the actions of the PCI host controller.