15 Aug
2011
15 Aug
'11
3:37 p.m.
On Fri, Aug 12, 2011 at 06:04:13PM -0400, Scott Jiang wrote:
some spi registers are 7bits global address + 1 bit r/w + 8 bits register address. soc cache layer can't support this kind well. so let codec driver read registers directly.
I have to agree with Barry, this changelog really doesn't explain what you're doing here at all clearly. You're adding 8, 16 read, that's it. This could also be used for reading volatile registers like interrupt status registers.
Stil, I've applied.