On Mon, Jul 23, 2012 at 02:51:48PM -0500, Pierre-Louis Bossart wrote:
On 7/23/2012 5:47 AM, Mark Brown wrote:
Don't drop CCs from replies.
I'm having a hard time relating this to what I was saying. The point here is that if the device keeps marching on consuming data (as most cyclic DMAs would) then there's still going to be an underrun even if there's a buffer that causes a delay in the user hearing it
Not necessarily. The DMA between system memory and DSP buffers need not work at a rate linked to the serial bit clock, they can be much faster, and actually they should to help put the system in a low power state rather than reading continuously from memory... what
I'm aware of this, thanks.
Vinod is trying to explain is that due to the bursty nature of data transfers inside the soc, we need to modify how the accounting is done.
Right, but this depends on the ability of the device to pause reading data when it reads up to the point where the application has written. This is a separate capability to any latency that's been added by the buffering, and most of the systems that have the buffering don't have this capability but instead either don't report the buffer or rely on the application being a full buffer ahead of the hardware.