20 Dec
2009
20 Dec
'09
7:58 p.m.
Hi,
On Sun, Dec 20, 2009 at 03:19:41PM +0100, Balbi Felipe (Nokia-D/Helsinki) wrote:
Hi,
On Fri, Dec 18, 2009 at 06:01:19PM +0100, ext Candelaria Villareal, Jorge wrote:
Mmm... But it _does_ have some breaks. Besides, I am still unsure that if structure should be used here. Code would be duplicated, for example, DN_IRQ_FULL and DN_IRQ_EMPTY share the same procedure to acknowledge the request.
quoting your switch for irq here:
switch (irq_status) {
case DN_IRQ_FULL:
case DN_IRQ_EMTPY:
dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status);
omap_mcpdm_reset(MCPDM_DOWNLINK, 1);
omap_mcpdm_set_downlink(mcpdm_irq->downlink);
omap_mcpdm_reset(MCPDM_DOWNLINK, 0);
break;
case DN_IRQ:
dev_dbg(mcpdm_irq->dev, "DN write request\n");
break;
case UP_IRQ_FULL:
case UP_IRQ_EMPTY:
dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status);
omap_mcpdm_reset(MCPDM_UPLINK, 1);
omap_mcpdm_set_uplink(mcpdm_irq->uplink);
omap_mcpdm_reset(MCPDM_UPLINK, 0);
break;
case UP_IRQ:
dev_dbg(mcpdm_irq->dev, "UP write request\n");
break;
}
what happens if you have both DN_IRQ_FULL and DN_IRQ_EMPTY at the same time ?
probably DN_IRQ_FULL and DN_IRQ_EMPTY won't happen at the same time, but maybe DN_IRQ_FULL and DN_IRQ. The point is that if two bits are enabled in the irq status register, the switch won't work.
--
balbi