According to spec, set to 1 is the enable of fractional devide or the clock can not be generated properly.
Signed-off-by: Dong Aisheng b29396@freescale.com Cc: Sascha Hauer s.hauer@pengutronix.de Reviewed-by: Wolfram Sang w.sang@pengutronix.de --- arch/arm/mach-mxs/clock-mx28.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 7b3657b..7954013 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -710,11 +710,11 @@ static int clk_misc_init(void)
/* SAIF has to use frac div for functional operation */ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0); - reg &= ~BM_CLKCTRL_SAIF0_DIV_FRAC_EN; + reg |= BM_CLKCTRL_SAIF0_DIV_FRAC_EN; __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1); - reg &= ~BM_CLKCTRL_SAIF1_DIV_FRAC_EN; + reg |= BM_CLKCTRL_SAIF1_DIV_FRAC_EN; __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
/*