14 Sep
2010
14 Sep
'10
2:55 p.m.
On Tue, Sep 14, 2010 at 03:45:25PM +0300, Jarkko Nikula wrote:
But is it marking register as volatile due 1-2 bits causing more problems if we don't cache rest of the r/w bits?
Depends on what else is there - ultimately if the chip has read support then the register cache is just a performance improvement.