/* VMID 2*4k; Soft VMID ramp enable */
- reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
- reg |= WM9081_VMID_RAMP | 0x6;
- snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
- snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
- WM9081_VMID_RAMP |
- WM9081_VMID_SEL_MASK,
- WM9081_VMID_RAMP | 0x6);
mdelay(100);
/* Normal bias enable & soft start off */
- reg &= ~WM9081_VMID_RAMP;
- snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
- snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
- WM9081_VMID_RAMP |
- WM9081_VMID_SEL_MASK, 0);
It's probably not trival why we need to clear WM9081_VMID_SEL_MASK bits here by looking at the patch. Looking at original code, you will know current code indeed clear WM9081_VMID_SEL_MASK bit here.
What current code does: 1. read WM9081_VMID_CONTROL register 2. write to WM9081_VMID_CONTROL register with setting WM9081_VMID_RAMP bit and setting WM9081_VMID_SEL_MASK bits to 0x6 (VMID 2*4k; Soft VMID ramp enable) 3. mdelay(100) 4. write to WM9081_VMID_CONTROL register with clearing WM9081_VMID_RAMP bit. Note: In this write, we do also clear WM9081_VMID_SEL_MASK bits because the register value of WM9081_VMID_SEL_MASK bits are clear when we read in "step1". In this case, the WM9081_VMID_SEL_MASK bits are clear because we clear WM9081_VMID_SEL_MASK bits in SND_SOC_BIAS_OFF. ( The default value is also zero for WM9081_VMID_SEL_MASK bits. )
While converting to snd_soc_update_bits here we actually do one more read. For the second call of snd_soc_update_bits, we need to explictly clear WM9081_VMID_SEL_MASK bits.
Regards, Axel