13 Sep
2013
13 Sep
'13
7:53 p.m.
On Fri, Sep 13, 2013 at 01:50:31PM +0300, Jyri Sarha wrote:
On 09/13/2013 01:34 PM, Mark Brown wrote:
OK, and presumably this is just part of the main McASP register block and doesn't need to go into DT?
Not really. For instance on am33xx SoCs the MPU usually accesses McASP registers trough L4 interconnect, which is not accessible by DMA controller. For DMA controller the data port is also mapped trough L3 bus to entirely different address and a simple register offset is not enough. Naturally this mapping may change SoC to SoC.
I see. I don't think this is a problem so long as the bindings are specified in a way that can be reused with dmaengine, which I'd guess ought to be the case if it's just specifying a physical address.