Hi Chancel,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on broonie-sound/for-next] [also build test ERROR on linus/master next-20221220] [cannot apply to v6.1] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Chancel-Liu/ASoC-dt-bindings-... base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next patch link: https://lore.kernel.org/r/20221222073618.1064415-3-chancel.liu%40nxp.com patch subject: [PATCH 2/3] ASoC: fsl_xcvr: Add support for i.MX93 platform config: i386-randconfig-a005-20221219 compiler: gcc-11 (Debian 11.3.0-8) 11.3.0 reproduce (this is a W=1 build): # https://github.com/intel-lab-lkp/linux/commit/496776030108247dd6b4eba85405ad... git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Chancel-Liu/ASoC-dt-bindings-fsl-xcvr-Add-compatible-string-for-i-MX93-platform/20221222-153903 git checkout 496776030108247dd6b4eba85405ad056b20c2a5 # save the config file mkdir build_dir && cp config build_dir/.config make W=1 O=build_dir ARCH=i386 olddefconfig make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot lkp@intel.com
All errors (new ones prefixed by >>):
ld: sound/soc/fsl/fsl_xcvr.o: in function `fsl_xcvr_runtime_resume':
sound/soc/fsl/fsl_xcvr.c:1391: undefined reference to `__udivdi3'
vim +1391 sound/soc/fsl/fsl_xcvr.c
1369 1370 static __maybe_unused int fsl_xcvr_runtime_resume(struct device *dev) 1371 { 1372 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1373 int ret; 1374 u64 rate, div; 1375 1376 ret = reset_control_assert(xcvr->reset); 1377 if (ret < 0) { 1378 dev_err(dev, "Failed to assert M0+ reset: %d\n", ret); 1379 return ret; 1380 } 1381 1382 ret = clk_prepare_enable(xcvr->ipg_clk); 1383 if (ret) { 1384 dev_err(dev, "failed to start IPG clock.\n"); 1385 return ret; 1386 } 1387 1388 /* set clk div for xcvr ip internal use */ 1389 if (xcvr->soc_data->spdif_only) { 1390 rate = clk_get_rate(xcvr->ipg_clk);
1391 div = rate / 1000000 - 1;
1392 ret = regmap_write(xcvr->regmap, FSL_XCVR_CLK_CTRL, div); 1393 if (ret < 0) { 1394 dev_err(dev, "Error while setting CLK_CTRL: %d\n", ret); 1395 return ret; 1396 } 1397 } 1398 1399 ret = clk_prepare_enable(xcvr->pll_ipg_clk); 1400 if (ret) { 1401 dev_err(dev, "failed to start PLL IPG clock.\n"); 1402 goto stop_ipg_clk; 1403 } 1404 1405 ret = clk_prepare_enable(xcvr->phy_clk); 1406 if (ret) { 1407 dev_err(dev, "failed to start PHY clock: %d\n", ret); 1408 goto stop_pll_ipg_clk; 1409 } 1410 1411 ret = clk_prepare_enable(xcvr->spba_clk); 1412 if (ret) { 1413 dev_err(dev, "failed to start SPBA clock.\n"); 1414 goto stop_phy_clk; 1415 } 1416 1417 regcache_cache_only(xcvr->regmap, false); 1418 regcache_mark_dirty(xcvr->regmap); 1419 ret = regcache_sync(xcvr->regmap); 1420 1421 if (ret) { 1422 dev_err(dev, "failed to sync regcache.\n"); 1423 goto stop_spba_clk; 1424 } 1425 1426 if (xcvr->soc_data->spdif_only) 1427 return 0; 1428 1429 ret = reset_control_deassert(xcvr->reset); 1430 if (ret) { 1431 dev_err(dev, "failed to deassert M0+ reset.\n"); 1432 goto stop_spba_clk; 1433 } 1434 1435 ret = fsl_xcvr_load_firmware(xcvr); 1436 if (ret) { 1437 dev_err(dev, "failed to load firmware.\n"); 1438 goto stop_spba_clk; 1439 } 1440 1441 /* Release M0+ reset */ 1442 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1443 FSL_XCVR_EXT_CTRL_CORE_RESET, 0); 1444 if (ret < 0) { 1445 dev_err(dev, "M0+ core release failed: %d\n", ret); 1446 goto stop_spba_clk; 1447 } 1448 1449 /* Let M0+ core complete firmware initialization */ 1450 msleep(50); 1451 1452 return 0; 1453 1454 stop_spba_clk: 1455 clk_disable_unprepare(xcvr->spba_clk); 1456 stop_phy_clk: 1457 clk_disable_unprepare(xcvr->phy_clk); 1458 stop_pll_ipg_clk: 1459 clk_disable_unprepare(xcvr->pll_ipg_clk); 1460 stop_ipg_clk: 1461 clk_disable_unprepare(xcvr->ipg_clk); 1462 1463 return ret; 1464 } 1465