Re: [v3 09/19] ASoC: mediatek: mt8186: support src in platform driver

Il 13/03/22 16:10, Jiaxin Yu ha scritto:

Add mt8186 src dai driver

Signed-off-by: Jiaxin Yu jiaxin.yu@mediatek.com

sound/soc/mediatek/mt8186/mt8186-dai-src.c | 726 +++++++++++++++++++++ 1 file changed, 726 insertions(+) create mode 100644 sound/soc/mediatek/mt8186/mt8186-dai-src.c

diff --git a/sound/soc/mediatek/mt8186/mt8186-dai-src.c b/sound/soc/mediatek/mt8186/mt8186-dai-src.c new file mode 100644 index 000000000000..0277cb0ad3f2 --- /dev/null +++ b/sound/soc/mediatek/mt8186/mt8186-dai-src.c @@ -0,0 +1,726 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// MediaTek ALSA SoC Audio DAI SRC Control +// +// Copyright (c) 2022 MediaTek Inc. +// Author: Jiaxin Yu jiaxin.yu@mediatek.com

+#include <linux/regmap.h> +#include "mt8186-afe-common.h" +#include "mt8186-interconnection.h"

..snip..

+static const unsigned int *get_iir_coeff(unsigned int rate_in,

• 			 unsigned int rate_out,
  

• 			 unsigned int *param_num)
  

+{

• if (rate_in == 32000 && rate_out == 16000) {

• *param_num = ARRAY_SIZE(src_iir_coeff_32_to_16);
  

• return src_iir_coeff_32_to_16;
  

• } else if (rate_in == 44100 && rate_out == 16000) {

• *param_num = ARRAY_SIZE(src_iir_coeff_44_to_16);
  

• return src_iir_coeff_44_to_16;
  

• } else if (rate_in == 44100 && rate_out == 32000) {

• *param_num = ARRAY_SIZE(src_iir_coeff_44_to_32);
  

• return src_iir_coeff_44_to_32;
  

• } else if ((rate_in == 48000 && rate_out == 16000) ||

•    (rate_in == 96000 && rate_out == 32000)) {
  

• *param_num = ARRAY_SIZE(src_iir_coeff_48_to_16);
  

• return src_iir_coeff_48_to_16;
  

• } else if (rate_in == 48000 && rate_out == 32000) {

• *param_num = ARRAY_SIZE(src_iir_coeff_48_to_32);
  

• return src_iir_coeff_48_to_32;
  

• } else if (rate_in == 48000 && rate_out == 44100) {

• *param_num = ARRAY_SIZE(src_iir_coeff_48_to_44);
  

• return src_iir_coeff_48_to_44;
  

• } else if (rate_in == 96000 && rate_out == 16000) {

• *param_num = ARRAY_SIZE(src_iir_coeff_96_to_16);
  

• return src_iir_coeff_96_to_16;
  

• } else if ((rate_in == 96000 && rate_out == 44100) ||

•    (rate_in == 48000 && rate_out == 22050)) {
  

• *param_num = ARRAY_SIZE(src_iir_coeff_96_to_44);
  

• return src_iir_coeff_96_to_44;
  

• }
• *param_num = 0;
• return NULL;

+}

+#define DEBUG_COEFF

I think that this debugging hackery unintentionally slipped through... or was that intentional? In the latter case, if you want to provide a way to debug that, you should use debugfs instead...

Please, either remove this debugging code, or use debugfs.

Thanks, Angelo

+static int mtk_set_src_1_param(struct mtk_base_afe *afe, int id) +{

• struct mt8186_afe_private *afe_priv = afe->platform_priv;
• struct mtk_afe_src_priv *src_priv = afe_priv->dai_priv[id];
• unsigned int iir_coeff_num;
• unsigned int iir_stage;
• int rate_in = src_priv->dl_rate;
• int rate_out = src_priv->ul_rate;
• unsigned int out_freq_mode = mtk_get_src_freq_mode(afe, rate_out);
• unsigned int in_freq_mode = mtk_get_src_freq_mode(afe, rate_in);
• /* set out freq mode */
• regmap_update_bits(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON3,

• 	   G_SRC_ASM_FREQ_4_MASK_SFT,
  

• 	   out_freq_mode << G_SRC_ASM_FREQ_4_SFT);
  

• /* set in freq mode */
• regmap_update_bits(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON4,

• 	   G_SRC_ASM_FREQ_5_MASK_SFT,
  

• 	   in_freq_mode << G_SRC_ASM_FREQ_5_SFT);
  

• regmap_write(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON5, 0x3f5986);
• regmap_write(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON5, 0x3f5987);
• regmap_write(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON6, 0x1fbd);
• regmap_write(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON2, 0);
• /* set iir if in_rate > out_rate */
• if (rate_in > rate_out) {

• int i;
  

+#ifdef DEBUG_COEFF

• int reg_val;
  

+#endif

• const unsigned int *iir_coeff = get_iir_coeff(rate_in, rate_out,
  

• 					      &iir_coeff_num);
  

• if (iir_coeff_num == 0 || !iir_coeff) {
  

• 	dev_err(afe->dev, "%s(), iir coeff error, num %d, coeff %p\n",
  

• 		__func__, iir_coeff_num, iir_coeff);
  

• 	return -EINVAL;
  

• }
  

• /* COEFF_SRAM_CTRL */
  

• regmap_update_bits(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON0,
  

• 		   G_SRC_COEFF_SRAM_CTRL_MASK_SFT,
  

• 		   BIT(G_SRC_COEFF_SRAM_CTRL_SFT));
  

• /* Clear coeff history to r/w coeff from the first position */
  

• regmap_update_bits(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON13,
  

• 		   G_SRC_COEFF_SRAM_ADR_MASK_SFT, 0);
  

• /* Write SRC coeff, should not read the reg during write */
  

• for (i = 0; i < iir_coeff_num; i++)
  

• 	regmap_write(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON12,
  

• 		     iir_coeff[i]);
  

+#ifdef DEBUG_COEFF

• regmap_update_bits(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON13,
  

• 		   G_SRC_COEFF_SRAM_ADR_MASK_SFT, 0);
  

• for (i = 0; i < iir_coeff_num; i++) {
  

• 	regmap_read(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON12,
  

• 		    &reg_val);
  

• 	dev_info(afe->dev, "%s(), i = %d, coeff = 0x%x\n",
  

• 		 __func__, i, reg_val);
  

• }
  

+#endif

• /* disable sram access */
  

• regmap_update_bits(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON0,
  

• 		   G_SRC_COEFF_SRAM_CTRL_MASK_SFT, 0);
  

• /* CHSET_IIR_STAGE */
  

• iir_stage = (iir_coeff_num / 6) - 1;
  

• regmap_update_bits(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON2,
  

• 		   G_SRC_CHSET_IIR_STAGE_MASK_SFT,
  

• 		   iir_stage << G_SRC_CHSET_IIR_STAGE_SFT);
  

• /* CHSET_IIR_EN */
  

• regmap_update_bits(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON2,
  

• 		   G_SRC_CHSET_IIR_EN_MASK_SFT,
  

• 		   BIT(G_SRC_CHSET_IIR_EN_SFT));
  

• } else {

• /* CHSET_IIR_EN off */
  

• regmap_update_bits(afe->regmap, AFE_GENERAL1_ASRC_2CH_CON2,
  

• 		   G_SRC_CHSET_IIR_EN_MASK_SFT, 0);
  

• }
• return 0;

+}

+static int mtk_set_src_2_param(struct mtk_base_afe *afe, int id) +{

• struct mt8186_afe_private *afe_priv = afe->platform_priv;
• struct mtk_afe_src_priv *src_priv = afe_priv->dai_priv[id];
• unsigned int iir_coeff_num;
• unsigned int iir_stage;
• int rate_in = src_priv->dl_rate;
• int rate_out = src_priv->ul_rate;
• unsigned int out_freq_mode = mtk_get_src_freq_mode(afe, rate_out);
• unsigned int in_freq_mode = mtk_get_src_freq_mode(afe, rate_in);
• /* set out freq mode */
• regmap_update_bits(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON3,

• 	   G_SRC_ASM_FREQ_4_MASK_SFT,
  

• 	   out_freq_mode << G_SRC_ASM_FREQ_4_SFT);
  

• /* set in freq mode */
• regmap_update_bits(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON4,

• 	   G_SRC_ASM_FREQ_5_MASK_SFT,
  

• 	   in_freq_mode << G_SRC_ASM_FREQ_5_SFT);
  

• regmap_write(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON5, 0x3f5986);
• regmap_write(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON5, 0x3f5987);
• regmap_write(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON6, 0x1fbd);
• regmap_write(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON2, 0);
• /* set iir if in_rate > out_rate */
• if (rate_in > rate_out) {

• int i;
  

+#ifdef DEBUG_COEFF

• int reg_val;
  

+#endif

• const unsigned int *iir_coeff = get_iir_coeff(rate_in, rate_out,
  

• 					      &iir_coeff_num);
  

• if (iir_coeff_num == 0 || !iir_coeff) {
  

• 	dev_err(afe->dev, "%s(), iir coeff error, num %d, coeff %p\n",
  

• 		 __func__, iir_coeff_num, iir_coeff);
  

• 	return -EINVAL;
  

• }
  

• /* COEFF_SRAM_CTRL */
  

• regmap_update_bits(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON0,
  

• 		   G_SRC_COEFF_SRAM_CTRL_MASK_SFT,
  

• 		   BIT(G_SRC_COEFF_SRAM_CTRL_SFT));
  

• /* Clear coeff history to r/w coeff from the first position */
  

• regmap_update_bits(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON13,
  

• 		   G_SRC_COEFF_SRAM_ADR_MASK_SFT, 0);
  

• /* Write SRC coeff, should not read the reg during write */
  

• for (i = 0; i < iir_coeff_num; i++)
  

• 	regmap_write(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON12,
  

• 		     iir_coeff[i]);
  

+#ifdef DEBUG_COEFF

• regmap_update_bits(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON13,
  

• 		   G_SRC_COEFF_SRAM_ADR_MASK_SFT, 0);
  

• for (i = 0; i < iir_coeff_num; i++) {
  

• 	regmap_read(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON12,
  

• 		    &reg_val);
  

• 	dev_info(afe->dev, "%s(), i = %d, coeff = 0x%x\n",
  

• 		 __func__, i, reg_val);
  

• }
  

+#endif

• /* disable sram access */
  

• regmap_update_bits(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON0,
  

• 		   G_SRC_COEFF_SRAM_CTRL_MASK_SFT, 0);
  

• /* CHSET_IIR_STAGE */
  

• iir_stage = (iir_coeff_num / 6) - 1;
  

• regmap_update_bits(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON2,
  

• 		   G_SRC_CHSET_IIR_STAGE_MASK_SFT,
  

• 		   iir_stage << G_SRC_CHSET_IIR_STAGE_SFT);
  

• /* CHSET_IIR_EN */
  

• regmap_update_bits(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON2,
  

• 		   G_SRC_CHSET_IIR_EN_MASK_SFT,
  

• 		   BIT(G_SRC_CHSET_IIR_EN_SFT));
  

• } else {

• /* CHSET_IIR_EN off */
  

• regmap_update_bits(afe->regmap, AFE_GENERAL2_ASRC_2CH_CON2,
  

• 		   G_SRC_CHSET_IIR_EN_MASK_SFT, 0);
  

• }
• return 0;

+}