From: Claudiu Beznea claudiu.beznea.uj@bp.renesas.com
Enable SSI3.
Reviewed-by: Geert Uytterhoeven geert+renesas@glider.be Signed-off-by: Claudiu Beznea claudiu.beznea.uj@bp.renesas.com ---
Changes in v4: - collected tags - dropped status for audio_clk2
Changes in v3: - none
Changes in v2: - none
arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 25 ++++++++++++++++++++ 1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 899d88467d79..1944468a2961 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -64,6 +64,10 @@ vccq_sdhi1: regulator-vccq-sdhi1 { }; };
+&audio_clk2 { + clock-frequency = <12288000>; +}; + &i2c0 { status = "okay";
@@ -105,6 +109,11 @@ power-monitor@44 { };
&pinctrl { + audio_clock_pins: audio-clock { + pins = "AUDIO_CLK1", "AUDIO_CLK2"; + input-enable; + }; + key-1-gpio-hog { gpio-hog; gpios = <RZG2L_GPIO(18, 0) GPIO_ACTIVE_LOW>; @@ -162,6 +171,13 @@ cd { pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */ }; }; + + ssi3_pins: ssi3 { + pinmux = <RZG2L_PORT_PINMUX(18, 2, 8)>, /* BCK */ + <RZG2L_PORT_PINMUX(18, 3, 8)>, /* RCK */ + <RZG2L_PORT_PINMUX(18, 4, 8)>, /* TXD */ + <RZG2L_PORT_PINMUX(18, 5, 8)>; /* RXD */ + }; };
&scif0 { @@ -182,3 +198,12 @@ &sdhi1 { max-frequency = <125000000>; status = "okay"; }; + +&ssi3 { + clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>, + <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>, + <&versa3 2>, <&audio_clk2>; + pinctrl-names = "default"; + pinctrl-0 = <&ssi3_pins>, <&audio_clock_pins>; + status = "okay"; +};