Re: [alsa-devel] ASOC: For SND_SOC_DAIFMT_IB_IF what is invert baseed on?

On Sun, 2008-10-26 at 00:31 +0800, Richard Zhao wrote:

Hi,

include/sound/soc.h /*

• DAI hardware signal inversions

*/ #define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bclk + frm */ #define SND_SOC_DAIFMT_NB_IF (1 << 8) /* normal bclk

• inv frm */

#define SND_SOC_DAIFMT_IB_NF (2 << 8) /* invert bclk

• nor frm */

#define SND_SOC_DAIFMT_IB_IF (3 << 8) /* invert bclk + frm */

What are frame cock and bit clock invert based on? I2S, PCM or some else bus protocols? Or just high level voltage or low level voltage?

Generic logic levels (high/low voltage) that can apply to I2S and PCM DAI's.

Liam