![](https://secure.gravatar.com/avatar/d28dfe03ea754ea1153719f4ced12649.jpg?s=120&d=mm&r=g)
6 Aug
2008
6 Aug
'08
10:47 a.m.
On Tue, Aug 05, 2008 at 02:37:31PM -0500, Timur Tabi wrote:
Signed-off-by: Timur Tabi timur@freescale.com
Applied, thanks.
* Wait until the SSI has filled its FIFO. Without this
* delay, ALSA complains about overruns. When the FIFO
* is full, the DMA controller initiates its first
* transfer. Until then, however, the DMA's DAR
* register is zero, which translates to an
* out-of-bounds pointer. This makes ALSA think an
* overrun has occurred. */
mdelay(1);
while (!(in_be32(&ssi->sisr) & CCSR_SSI_SISR_RFF0));
It'd be nice to have a timeout here in case the FIFO never fills.