On Wed, 09 Dec 2015 12:14:55 +0100, Subhransu S. Prusty wrote:
On Wed, Dec 09, 2015 at 09:13:56AM +0100, Takashi Iwai wrote:
On Wed, 09 Dec 2015 09:03:38 +0100, Subhransu S. Prusty wrote:
Hi Takashi,
> > Though, the max number of converters is limited, thus what you can > > actually use is defined by this constraint. Due to this, we'll likely > > manage MST for the legacy HDA by assigning MST devs dynamically to > > pins in a certain procedure to make things compatible. > > but how many MST devs are you going to create?
This is exactly the point: for the legacy HDA, instead of creating the entry for each MST devices, they are assigned dynamically to PCM at activation. So the number of devices exposed to user-space is limited -- or better to say, user-space won't notice the difference.
And how many PCMs are you proposing for MST?
5 for Intel, i.e. Nconv * 2 - 1. This could be even Nconv, but we provide the reserved slots just for the compatible behavior that assumes the static pin/slot assignment.
How is Nconv * 2 - 1 PCMs are derived? Lets assume, there are 3 cvts and 4pins, I think it will not work.
We're talking about Intel case, right? Then both numbers are same.
Yes that's true. But was wondering what if it changes in future.
Well, then the formula will be changed, too :) As mentioned, the number of PCMs doesn't have to be changed in theory. The point is only to map the active connection to the available PCM slot dynamically, then this is notified to user-space. We reserve a few more PCM slots than of now, but it's just for subtle compatibility reason.
Takashi