On Fri, Aug 6, 2010 at 9:18 AM, Seungwhan Youn sw.youn@samsung.com wrote:
This patch adds to support additional ADC clock source setting with R8 register for CLKSRC on wm8580.
Signed-off-by: Seungwhan Youn sw.youn@samsung.com
sound/soc/codecs/wm8580.c | 33 +++++++++++++++++++++++++++++++++ sound/soc/codecs/wm8580.h | 16 +++++++++------- 2 files changed, 42 insertions(+), 7 deletions(-)
diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c index c3571ee..e342da5 100644 --- a/sound/soc/codecs/wm8580.c +++ b/sound/soc/codecs/wm8580.c @@ -110,6 +110,12 @@ #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
+#define WM8580_CLKSEL_ADC_CLKSEL_MASK 0x0c +#define WM8580_CLKSEL_ADC_CLKSEL_ADCMCLK 0x00 +#define WM8580_CLKSEL_ADC_CLKSEL_PLLA 0x04 +#define WM8580_CLKSEL_ADC_CLKSEL_PLLB 0x08 +#define WM8580_CLKSEL_ADC_CLKSEL_MCLK 0x0c
/* AIF control 1 (registers 9h-bh) */ #define WM8580_AIF_RATE_MASK 0x7 #define WM8580_AIF_RATE_128 0x0 @@ -672,6 +678,33 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai, snd_soc_write(codec, WM8580_PLLB4, reg); break;
- case WM8580_ADC_CLKSEL:
- reg = snd_soc_read(codec, WM8580_CLKSEL);
- reg &= ~WM8580_CLKSEL_ADC_CLKSEL_MASK;
- switch (div) {
- case WM8580_CLKSRC_ADCMCLK:
- reg |= WM8580_CLKSEL_ADC_CLKSEL_ADCMCLK;
- break;
- case WM8580_CLKSRC_MCLK:
- reg |= WM8580_CLKSEL_ADC_CLKSEL_MCLK;
- break;
- case WM8580_CLKSRC_PLLA:
- reg |= WM8580_CLKSEL_ADC_CLKSEL_PLLA;
- break;
- case WM8580_CLKSRC_PLLB:
- reg |= WM8580_CLKSEL_ADC_CLKSEL_PLLB;
- break;
- default:
- return -EINVAL;
- }
- snd_soc_write(codec, WM8580_CLKSEL, reg);
- break;
default: return -EINVAL; } diff --git a/sound/soc/codecs/wm8580.h b/sound/soc/codecs/wm8580.h index 0dfb5dd..aeb65ef 100644 --- a/sound/soc/codecs/wm8580.h +++ b/sound/soc/codecs/wm8580.h @@ -20,13 +20,15 @@
#define WM8580_MCLK 1 #define WM8580_DAC_CLKSEL 2 -#define WM8580_CLKOUTSRC 3
-#define WM8580_CLKSRC_MCLK 1 -#define WM8580_CLKSRC_PLLA 2 -#define WM8580_CLKSRC_PLLB 3 -#define WM8580_CLKSRC_OSC 4 -#define WM8580_CLKSRC_NONE 5 +#define WM8580_ADC_CLKSEL 3 +#define WM8580_CLKOUTSRC 4
+#define WM8580_CLKSRC_MCLK 1 +#define WM8580_CLKSRC_ADCMCLK 2 +#define WM8580_CLKSRC_PLLA 3 +#define WM8580_CLKSRC_PLLB 4 +#define WM8580_CLKSRC_OSC 5 +#define WM8580_CLKSRC_NONE 6
#define WM8580_DAI_PAIFRX 0 #define WM8580_DAI_PAIFTX 1
This is OK. Though I don't remember why it wasn't accepted when I submitted a few months ago.