On Wed, 22 Jun 2011 10:26:28 -0500 Philip Chu Philip.Chu@logicpd.com wrote:
Thanks for your help.
How big is the chance that McBSP will have samples remaining in its shift registers, not to its FIFO until next time it receives new data samples?
I suppose none if McBSP framesize (wlen * channels) number of bitclock cycles (+ possible 1-bit data delay) are received after framesync.
My PCM DMA is running in element mode so it sets up FIFO threshold as 1 (0 in the register). That means FIFO should pass the data as long as it sees them coming.
Before the very first DMA ISR (completed a period of data transfer by DMA), the DMA pointer is a void number, I think it means DMA has not ever completed one entire period transfer yet. My suspection is, does DMA need some time to be ready for receiving data from McBSP's DMA event? If it does need some time, then the very first a couple of sample(s) from McBSP could be missed.
Indeed, this is actually strange that DMA pointer is not updated. How big is your period size? Is it smaller than DMA burst size which is set to 64 bytes in sound/soc/omap/omap-pcm.c? I'm not sure does the DMA use burst transfer in element mode but non-updating pointer is kind of indicating that there is neither DMA transfer going on until enough data is received.