Hi Jiada
There are AVB Counter Clocks in ADG, each clock has 12bits integral and 8 bits fractional dividers which operates with S0D1ϕ clock.
This patch registers 8 AVB Counter Clocks when clock-cells of rcar_sound node is 2,
Signed-off-by: Jiada Wang jiada_wang@mentor.com
+static void clk_avb_div_write(struct rsnd_adg *adg, u32 data, unsigned int idx)
(snip)
+static u32 clk_avb_div_read(struct rsnd_adg *adg, unsigned int idx)
As I mentioned before, I think we can avoid confusable parameter by
static void clk_avb_div_write(struct clk_avb *avb, u32 data) static u32 clk_avb_div_read(struct clk_avb)
div = clk_avb_div_read(avb); clk_avb_div_write(avb, val | div);
+static struct clk *clk_register_avb(struct device *dev, struct rsnd_adg *adg,
unsigned int id, spinlock_t *lock)+{
- struct clk_init_data init;
- struct clk_avb *avb;
- struct clk *clk;
- char name[8];
- const char *parent_name;
- if (IS_ERR(adg->clkadg))
return ERR_PTR(-ENODEV);
I think adg->clkadg will never hit to IS_ERR(). It will have NULL or correct pointer.
clk = devm_clk_get(dev, "adg"); if (!IS_ERR(clk)) adg->clkadg = clk;
And this "adg" clock is strange. see below
- avb = devm_kzalloc(dev, sizeof(*avb), GFP_KERNEL);
- if (!avb)
return ERR_PTR(-ENOMEM);- parent_name = __clk_get_name(adg->clkadg);
This parent_name is very strange to me. AVB parent clk is "AUDIO_CLK_A/B/C/I" (= clk_a/b/c/i in this driver) or "AUDIO_CLK_OUT_A/B/C/D" (= audio_clkout/1/2/3 in this driver). And we don't have "adg" clock. Please double check it.
Best regards --- Kuninori Morimoto