As indicated in the datasheet, a 10ms delay must be observed after programming the divisors.
The lack of delay prevents the codec to work properly and the playback appears extremely slow and totally un-audible on a custom sama5 based board.
Signed-off-by: Miquel Raynal miquel.raynal@bootlin.com --- sound/soc/codecs/tlv320aic32x4-clk.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/sound/soc/codecs/tlv320aic32x4-clk.c b/sound/soc/codecs/tlv320aic32x4-clk.c index 156c153c12ab..2f78e6820c75 100644 --- a/sound/soc/codecs/tlv320aic32x4-clk.c +++ b/sound/soc/codecs/tlv320aic32x4-clk.c @@ -230,7 +230,14 @@ static int clk_aic32x4_pll_set_rate(struct clk_hw *hw, if (ret < 0) return -EINVAL;
- return clk_aic32x4_pll_set_muldiv(pll, &settings); + ret = clk_aic32x4_pll_set_muldiv(pll, &settings); + if (ret) + return ret; + + /* 10ms is the delay to wait before the clocks are stable */ + msleep(10); + + return 0; }
static int clk_aic32x4_pll_set_parent(struct clk_hw *hw, u8 index)