Mark,
On 2012-11-13 Mark Brown wrote:
snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 0x30,
/** GPIO1 is used for OPCLK, reconfigure into default* mode as input - before configuring OPCLKDIV and PLL*/snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 0x37, (opclk_div - 1) << 4);Previously we weren't changing the pin mode at all, we were only updating the bitfield that contains OPCLK. With your change we will also change the pin mode to input, but if the pin is doing any form of output (or anything other than input mode) I'd expect this to at least glitch things which seems actively harmful. Why is it being set up as an input? Though I have to say that all this handling of the pin in the existing driver looks at best odd.
Your changelog describes what you're doing but not what is being fixed...
The issue was in the following snippet:
@@ -529,9 +533,6 @@ static int wm8978_configure_pll(struct snd_soc_codec *codec) return idx;
wm8978->mclk_idx = idx; - - /* GPIO1 into default mode as input - before configuring PLL */ - snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0); } else { return -EINVAL; }
This bit of code was always reconfiguring the pin to input when it was known that OPCLK was not needed. I am using GPIO1 to enable an amplifier, so I do not want it reconfigured. I moved the reconfiguring of GPIO1 to the block of code under "if (f_opclk)", so we can safely assume that that pin is not being used for something else.
However, I agree that the handling of the pin is odd. Does OPCLK really need to be reconfigured as input whenever the PLL values are updated? I didn't see anything in the user manual to suggest that that needed to be done.
Eric
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