On Thu, Dec 26, 2013 at 10:57:22AM +0800, Xiubo Li wrote:
This is maybe one bug or a limitation of the hardware that the {T,R}CR2's Synchronous Mode bits must be set as late as possible, or the SAI device maybe hanged up, and there has not any explaination about this limitation in the SAI Data Sheet.
If they really should be set as late as possible then I'd expect them to be being set in the trigger function, that's what gets called as the audio actually starts streaming. This is moving it to the startup function which is one of the first things that happens during audio stream setup so presumably makes things worse.
Also...
@@ -62,6 +62,7 @@ static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, reg_cr2 = FSL_SAI_RCR2;
val_cr2 = sai_readl(sai, sai->base + reg_cr2);
- switch (clk_id) { case FSL_SAI_CLK_BUS: val_cr2 &= ~FSL_SAI_CR2_MSEL_MASK;
@@ -82,6 +83,7 @@ static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, default: return -EINVAL; }
sai_writel(sai, val_cr2, sai->base + reg_cr2);
return 0;
These appear to be unrelated changes - please send as a separate patch if they're useful.