On Wed, 22 Oct 2008 15:26:36 +0530 "ext Arun KS" getarunks@gmail.com wrote:
/* Generic McBSP register settings */ regs->spcr2 |= XINTM(3) | FREE;@@ -293,6 +307,8 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, /* 0-bit data delay */ regs->rcr2 |= RDATDLY(0); regs->xcr2 |= XDATDLY(0);
/* Invert bit clock and FS polarity configuration for DSP_A */temp_fmt ^= SND_SOC_DAIFMT_IB_IF;Can you tell me why this is done here? This is modifying what machine driver has chosen. AM I missing something?
Since as a McBSP sense, the normal polarities in DSP format (or according to AIC33 DSP mode...) were different than in I2S. Idea is to keep codec and cpu configuration in sync in the machine driver, i.e. same bit clock and frame sync polarity configuration
/* Set codec DAI configuration */ err = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
/* Set cpu DAI configuration */ err = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
Jarkko