On 04/21, Sylwester Nawrocki wrote:
The existing enable/disable ops for PLL35XX are made more generic and used also for PLL36XX. This fixes issues in the kernel with PLL36XX PLLs when the PLL has not been already enabled by bootloader.
Signed-off-by: Sylwester Nawrocki s.nawrocki@samsung.com
drivers/clk/samsung/clk-pll.c | 85 +++++++++++++++++++++++++------------------ 1 file changed, 49 insertions(+), 36 deletions(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 5229089..10c76eb 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -23,6 +23,10 @@ struct samsung_clk_pll { struct clk_hw hw; void __iomem *lock_reg; void __iomem *con_reg;
- /* PLL enable control bit offset in @con_reg register */
- unsigned short enable_offs;
- /* PLL lock status bit offset in @con_reg register */
- unsigned short lock_offs; enum samsung_pll_type type; unsigned int rate_count; const struct samsung_pll_rate_table *rate_table;
@@ -61,6 +65,34 @@ static long samsung_pll_round_rate(struct clk_hw *hw, return rate_table[i - 1].rate; }
+static int samsung_pll3xxx_enable(struct clk_hw *hw) +{
- struct samsung_clk_pll *pll = to_clk_pll(hw);
- u32 tmp;
- tmp = readl_relaxed(pll->con_reg);
- tmp |= BIT(pll->enable_offs);
- writel_relaxed(tmp, pll->con_reg);
- /* wait lock time */
- do {
cpu_relax();tmp = readl_relaxed(pll->con_reg);- } while (!(tmp & BIT(pll->lock_offs)));
Not a problem with this patch because we're moving code around, but this is a potential infinite loop that should have some sort of timeout so we don't sit here forever trying to see a bit toggle.