18 Apr
2008
18 Apr
'08
10:13 a.m.
Hi Jarkko,
On Fri, Apr 18, 2008 at 10:59:08AM +0300, Jarkko Nikula wrote:
I had a quick look to your patch and AIC33 spec.
Is this the same than 256-clock transfer mode?
No, the 256-clock mode is for output only, while in my setup the TLV is in slave mode. I attached this chip to the I2S output of an PXA270 which always outputs sample rate * 256 as system clock. In this very case, the PLL can be bypassed by selecting the left path described on page 27.
Should you set the bit 3 in AIC3X_ASD_INTF_CTRLB in this case? Should you also still write the AIC3X_SAMPLE_RATE_SEL_REG?
AIC3X_SAMPLE_RATE_SEL_REG defaults to 0 which is what I want in this case. Thus, I don't have to write it.
Daniel