On 17/05/2024 11:45, Shengjiu Wang wrote:
In order to support the MQS module on i.MX95, a new property "fsl,mqs-ctrl" needs to be added, as there are two MQS instances on the i.MX95 platform, the definition of bit positions in the control register is different. This new property is to distinguish these two instances.
Without this property, the difference of platforms except the i.MX95 was handled by the driver itself. But this new property can also be used for previous platforms.
The MQS only has one control register, the register may be in General Purpose Register memory space, or MQS its own memory space, or controlled by System Manager. The bit position in the register may be different for each platform, there are four parts (bits for module enablement, bits for reset, bits for oversampling ratio, bits for divider ratio). This new property includes all these things.
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clocks: minItems: 1 @@ -45,6 +46,22 @@ properties: resets: maxItems: 1
- fsl,mqs-ctrl:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 6
- maxItems: 6
- description: |
Contains the control register information, defined as,Cell #1: register type0 - the register in owned register map1 - the register in general purpose register map2 - the register in control of system managerCell #2: offset of the control register from the sysconCell #3: shift bits for module enable bitCell #4: shift bits for reset bitCell #5: shift bits for oversampling ratio bitCell #6: shift bits for divider ratio control bit
Thanks for detailed explanation in commit msg, but no, please do not describe layout of registers in DTS. For the syscon phandles, you can pass an argument (although not 6 arguments...). Usually this is enough. For some cases, like you have differences in capabilities of this device or its programming model, maybe you need different compatible.
If these are different capabilities, sometimes new properties are applicable (describing hardware, not register bits...).
Best regards, Krzysztof