8 Mar
2021
8 Mar
'21
10:46 a.m.
On Mon, Mar 08, 2021 at 10:34:37AM +0800, Shengjiu Wang wrote:
With S20_3LE format case, the sysclk = rate * 384, the bclk = rate * 20 * 2, there is no proper bclk divider for 384 / 40, because current condition needs exact match. So driver fails to configure the clocking:
wm8962 3-001a: Unsupported BCLK ratio 9
Fix this by relaxing bitclk divider searching, so that when no exact value can be derived from sysclk pick the closest value greater than expected bitclk.
Signed-off-by: Shengjiu Wang shengjiu.wang@nxp.com Reviewed-by: Daniel Baluta daniel.baluta@nxp.com
Acked-by: Charles Keepax ckeepax@opensource.cirrus.com
Thanks, Charles