Hi Srinivas,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0]
url: https://github.com/intel-lab-lkp/linux/commits/Srinivas-Kandagatla/ASoC-code... base: 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0 patch link: https://lore.kernel.org/r/20240618-lpass-wsa-vi-v1-2-416a6f162c81%40linaro.o... patch subject: [PATCH 2/2] ASoC: codecs:lpass-wsa-macro: Fix logic of enabling vi channels config: i386-buildonly-randconfig-002-20240619 (https://download.01.org/0day-ci/archive/20240619/202406191005.yMuWtspN-lkp@i...) compiler: clang version 18.1.5 (https://github.com/llvm/llvm-project 617a15a9eac96088ae5e9134248d8236e34b91b1) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240619/202406191005.yMuWtspN-lkp@i...)
If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot lkp@intel.com | Closes: https://lore.kernel.org/oe-kbuild-all/202406191005.yMuWtspN-lkp@intel.com/
All warnings (new ones prefixed by >>):
sound/soc/codecs/lpass-wsa-macro.c:999:2: warning: unannotated fall-through between switch labels [-Wimplicit-fallthrough] 999 | default: | ^ sound/soc/codecs/lpass-wsa-macro.c:999:2: note: insert 'break;' to avoid fall-through 999 | default: | ^ | break;
sound/soc/codecs/lpass-wsa-macro.c:1238:6: warning: variable 'tx_reg0' set but not used [-Wunused-but-set-variable]
1238 | u32 tx_reg0, tx_reg1; | ^
sound/soc/codecs/lpass-wsa-macro.c:1238:15: warning: variable 'tx_reg1' set but not used [-Wunused-but-set-variable]
1238 | u32 tx_reg0, tx_reg1; | ^ 3 warnings generated.
vim +/tx_reg0 +1238 sound/soc/codecs/lpass-wsa-macro.c
0c27e978419e7e Srinivas Kandagatla 2024-06-18 1231 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1232 static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w, 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1233 struct snd_kcontrol *kcontrol, 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1234 int event) 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1235 { 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1236 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1237 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 @1238 u32 tx_reg0, tx_reg1; 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1239 u32 rate_val; 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1240 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1241 switch (wsa->pcm_rate_vi) { 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1242 case 8000: 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1243 rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K; 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1244 break; 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1245 case 16000: 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1246 rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_16K; 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1247 break; 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1248 case 24000: 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1249 rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_24K; 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1250 break; 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1251 case 32000: 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1252 rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_32K; 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1253 break; 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1254 case 48000: 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1255 rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_48K; 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1256 break; 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1257 default: 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1258 rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K; 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1259 break; 2881dae5fbb091 Srinivas Kandagatla 2024-06-18 1260 } 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1261 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1262 if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1263 tx_reg0 = CDC_WSA_TX0_SPKR_PROT_PATH_CTL; 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1264 tx_reg1 = CDC_WSA_TX1_SPKR_PROT_PATH_CTL; 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1265 } else if (test_bit(WSA_MACRO_TX1, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1266 tx_reg0 = CDC_WSA_TX2_SPKR_PROT_PATH_CTL; 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1267 tx_reg1 = CDC_WSA_TX3_SPKR_PROT_PATH_CTL; 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1268 } 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1269 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1270 switch (event) { 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1271 case SND_SOC_DAPM_POST_PMU: 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1272 /* Enable V&I sensing */ 0c27e978419e7e Srinivas Kandagatla 2024-06-18 1273 wsa_macro_enable_disable_vi_feedback(component, true, rate_val); 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1274 break; 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1275 case SND_SOC_DAPM_POST_PMD: 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1276 /* Disable V&I sensing */ 0c27e978419e7e Srinivas Kandagatla 2024-06-18 1277 wsa_macro_enable_disable_vi_feedback(component, false, rate_val); 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1278 break; 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1279 } 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1280 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1281 return 0; 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1282 } 2c4066e5d428d4 Srinivas Kandagatla 2020-11-05 1283