On Tue, Jun 11, 2013 at 01:01:57PM -0300, Fabio Estevam wrote:
On 06/11/2013 12:22 PM, Oskar Schirmer wrote:
According to documentation bit 3:2 in register SSS_CTRL are reserved and zero, so initially setting the register to 0x0008 does not make much sense. Instead, bit 4 should be marked set, as this is the power up default.
Further, mask computation in declarative part is obviously wrong: Fix FRAC DIVISOR to provide an 11 bit mask correctly.
Signed-off-by: Oskar Schirmer oskar@scara.com Tested-by: Fabio Estevam fabio.estevam@freescale.com
Looks good, but please copy Mark Brown. Just added him in Cc now.
Please also use subject lines matching the normal style for the subsystem. I can't apply this unless someone sends me a copy properly (not quoted and so on).