On 02/24/2012 09:53 AM, javier Martin wrote:
If TFSI bit is 1, frame clock is active high. If TFSI bit is 0, frame clock is active low.
In the piece of code I've shown to you, when someone configures (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF) he's really selecting an active high frame clock when the standard says just the opposite (wm8974 datasheet p50).
We had similar issues on OMAP McBSP in the past. If you take a look at the omap-mcbsp.c: omap_mcbsp_dai_set_dai_fmt() function we have inv_fs variable to handle such a case. We do the FS/BCLK configuration only in DAIFMT_INV config phase. The FS active level is different in these formats. We invert the FS based on the used format (LEFT/RIGHT just, DSP). The DAIFMT_INV switch configures according to I2S, but we invert the FS if we are in DSP, Justified modes afterwards.
there is at least one platform relying on this misleading behavior that I can't test: http://lxr.linux.no/#linux+v3.2.7/sound/soc/imx/wm1133-ev1.c#L81
That was correct at the time it was written, though the code has changed since then and I don't know when it was last retested. Of course depending on the signal it may interoperate well even if the setup isn't actually correct. I'd just fix the driver and if it works for yours it's probably OK for that board too.
It is not one but two boards that are affected: http://lxr.linux.no/#linux+v3.2.7/sound/soc/imx/wm1133-ev1.c#L81 http://lxr.linux.no/#linux+v3.2.7/sound/soc/imx/eukrea-tlv320.c#L32
If I fixed the bug in the SSI I would break both of them, since I would be changing frame clock polarity.
I don't think it is going to break. I would guess that the channels are swapped on these machines at the moment. If you correct the CPU dai driver the only thing that will happen is that the channels will jump in their correct place.