9 Jun
2016
9 Jun
'16
7:41 p.m.
On Thu, Jun 09, 2016 at 07:39:06PM +0200, Lars-Peter Clausen wrote:
Multiple devices from the ADAU family share the same PLL structure and configuration register layout. Introduce a new helper module that can be used to calculated the PLL configuration registers based on a specified input frequency and the desired output frequency of the PLL.
Sounds like we may be heading towards an MFD with a clock driver here?