23 Jul
2012
23 Jul
'12
9:51 p.m.
On 7/23/2012 5:47 AM, Mark Brown wrote:
I'm having a hard time relating this to what I was saying. The point here is that if the device keeps marching on consuming data (as most cyclic DMAs would) then there's still going to be an underrun even if there's a buffer that causes a delay in the user hearing it
Not necessarily. The DMA between system memory and DSP buffers need not work at a rate linked to the serial bit clock, they can be much faster, and actually they should to help put the system in a low power state rather than reading continuously from memory... what Vinod is trying to explain is that due to the bursty nature of data transfers inside the soc, we need to modify how the accounting is done.