On 2016-12-09 02:25, Stephen Boyd wrote:
On 12/07, Irina Tirdea wrote:
The BayTrail and CherryTrail platforms provide platform clocks through their Power Management Controller (PMC).
The SoC supports up to 6 clocks (PMC_PLT_CLK[5:0]) with a frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail an a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks are available for general system use, where appropriate, and each have Control & Frequency register fields associated with them.
For example, the usage for platform clocks suggested in the datasheet is the following: PLT_CLK[2:0] - Camera PLT_CLK[3] - Audio Codec PLT_CLK[4] - PLT_CLK[5] - COMMs Signed-off-by: Irina Tirdea irina.tirdea@intel.com Signed-off-by: Pierre-Louis Bossart <pierre- louis.bossart@linux.intel.com> --- drivers/clk/x86/Makefile | 1 + drivers/clk/x86/clk-byt-plt.c | 380
++++++++++++++++++++++++++
Is it possible to split the clk part from the platform part? I'd like to merge just the clk part if possible into the clk tree.
It would be great to have the clk part merged. I'll put the code in a separate patch.
Thanks, Irina