Nicolin, thank you very much.
On 03/17/2015 08:38 AM, Nicolin Chen wrote:
On Tue, Mar 17, 2015 at 08:24:27AM +0800, Xuebing Wang wrote:
- As pll4_main_clk is global for all 3 SSIs, I think that we can *not* use
8k for ssi1 and 44.1k for ssi2, right? Because 8k and 44.1k requires different pll4 clock, right?
True.
-- However, as 48k, 32k, 16k, 8k can use same pll4, thus different SSIcan use different sampling rate in this subset (48k, 32k, 16k, 8k). -- Same principle applies for 44.1k, 22.050, 11.025 subset of sampling rates.
Correct. You need to choose 48K-group or 44.1K-group if only using PLL4.
If you are so obsessed with full sample rate support in hardware level, you might need to do a trade-off like sacrificing video function -- you would then be allowed to use PLL5 to forge a rate for another rate group.
I forgot if PLL3, another possible parent clock of SSI, is suitable for one of the groups. You may also take a look at it.
Nicolin