Hi Herve,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on broonie-sound/for-next] [also build test ERROR on robh/for-next powerpc/next powerpc/fixes linus/master v6.2-rc2 next-20230106] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Herve-Codina/dt-bindings-soc-... base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next patch link: https://lore.kernel.org/r/20230106132951.392271-3-herve.codina%40bootlin.com patch subject: [PATCH 02/10] soc: fsl: qe: Add support for TSA config: m68k-allmodconfig compiler: m68k-linux-gcc (GCC) 12.1.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/intel-lab-lkp/linux/commit/2f330c694ec5018a16972be5314997... git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Herve-Codina/dt-bindings-soc-fsl-cpm_qe-Add-TSA-controller/20230106-213320 git checkout 2f330c694ec5018a16972be5314997b4da85385a # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=m68k olddefconfig COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=m68k SHELL=/bin/bash drivers/soc/fsl/qe/
If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot lkp@intel.com
All errors (new ones prefixed by >>):
drivers/soc/fsl/qe/tsa.c: In function 'tsa_connect':
drivers/soc/fsl/qe/tsa.c:149:9: error: implicit declaration of function 'clrsetbits_be32' [-Werror=implicit-function-declaration]
149 | clrsetbits_be32(tsa->si_regs + TSA_SICR, clear, set); | ^~~~~~~~~~~~~~~ drivers/soc/fsl/qe/tsa.c: In function 'tsa_add_entry':
drivers/soc/fsl/qe/tsa.c:288:17: error: implicit declaration of function 'clrbits32' [-Werror=implicit-function-declaration]
288 | clrbits32(area->last_entry, TSA_SIRAM_ENTRY_LAST); | ^~~~~~~~~ cc1: some warnings being treated as errors
vim +/clrsetbits_be32 +149 drivers/soc/fsl/qe/tsa.c
125 126 int tsa_connect(struct tsa *tsa, unsigned int cell_index) 127 { 128 u32 clear; 129 u32 set; 130 131 switch (cell_index) { 132 case FSL_CPM_TSA_SCC2: 133 clear = TSA_SICR_SCC2(TSA_SICR_SCC_MASK); 134 set = TSA_SICR_SCC2(TSA_SICR_SCC_SCX_TSA); 135 break; 136 case FSL_CPM_TSA_SCC3: 137 clear = TSA_SICR_SCC3(TSA_SICR_SCC_MASK); 138 set = TSA_SICR_SCC3(TSA_SICR_SCC_SCX_TSA); 139 break; 140 case FSL_CPM_TSA_SCC4: 141 clear = TSA_SICR_SCC4(TSA_SICR_SCC_MASK); 142 set = TSA_SICR_SCC4(TSA_SICR_SCC_SCX_TSA); 143 break; 144 default: 145 dev_err(tsa->dev, "Unsupported cell-index %u\n", cell_index); 146 return -EINVAL; 147 } 148
149 clrsetbits_be32(tsa->si_regs + TSA_SICR, clear, set);
150 return 0; 151 } 152 EXPORT_SYMBOL(tsa_connect); 153 154 int tsa_disconnect(struct tsa *tsa, unsigned int cell_index) 155 { 156 u32 clear; 157 158 switch (cell_index) { 159 case 2: 160 clear = TSA_SICR_SCC2(TSA_SICR_SCC_MASK); 161 break; 162 case 3: 163 clear = TSA_SICR_SCC3(TSA_SICR_SCC_MASK); 164 break; 165 case 4: 166 clear = TSA_SICR_SCC4(TSA_SICR_SCC_MASK); 167 break; 168 default: 169 dev_err(tsa->dev, "Unsupported cell-index %u\n", cell_index); 170 return -EINVAL; 171 } 172 173 clrsetbits_be32(tsa->si_regs + TSA_SICR, clear, 0); 174 return 0; 175 } 176 EXPORT_SYMBOL(tsa_disconnect); 177 178 int tsa_get_info(struct tsa *tsa, unsigned int cell_id, struct tsa_cell_info *info) 179 { 180 if (cell_id >= FSL_CPM_TSA_NBCELL) 181 return -EINVAL; 182 183 memcpy(info, &tsa->cell_infos[cell_id], sizeof(*info)); 184 return 0; 185 } 186 EXPORT_SYMBOL(tsa_get_info); 187 188 static void tsa_init_entries_area(struct tsa *tsa, struct tsa_entries_area *area, 189 u32 tdms, u32 tdm_id, bool is_rx) 190 { 191 resource_size_t quarter; 192 resource_size_t half; 193 194 quarter = tsa->si_ram_sz/4; 195 half = tsa->si_ram_sz/2; 196 197 if (tdms == BIT(TSA_TDMA)) { 198 /* Only TDMA */ 199 if (is_rx) { 200 /* First half of si_ram */ 201 area->entries_start = tsa->si_ram; 202 area->entries_next = area->entries_start + half; 203 area->last_entry = NULL; 204 } else { 205 /* Second half of si_ram */ 206 area->entries_start = tsa->si_ram + half; 207 area->entries_next = area->entries_start + half; 208 area->last_entry = NULL; 209 } 210 } else { 211 /* Only TDMB or both TDMs */ 212 if (tdm_id == TSA_TDMA) { 213 if (is_rx) { 214 /* First half of first half of si_ram */ 215 area->entries_start = tsa->si_ram; 216 area->entries_next = area->entries_start + quarter; 217 area->last_entry = NULL; 218 } else { 219 /* First half of second half of si_ram */ 220 area->entries_start = tsa->si_ram + (2 * quarter); 221 area->entries_next = area->entries_start + quarter; 222 area->last_entry = NULL; 223 } 224 } else { 225 if (is_rx) { 226 /* Second half of first half of si_ram */ 227 area->entries_start = tsa->si_ram + quarter; 228 area->entries_next = area->entries_start + quarter; 229 area->last_entry = NULL; 230 } else { 231 /* Second half of second half of si_ram */ 232 area->entries_start = tsa->si_ram + (3 * quarter); 233 area->entries_next = area->entries_start + quarter; 234 area->last_entry = NULL; 235 } 236 } 237 } 238 } 239 240 static const char *tsa_cell_id2name(struct tsa *tsa, u32 cell_id) 241 { 242 switch (cell_id) { 243 case FSL_CPM_TSA_NU: return "Not used"; 244 case FSL_CPM_TSA_SCC2: return "SCC2"; 245 case FSL_CPM_TSA_SCC3: return "SCC3"; 246 case FSL_CPM_TSA_SCC4: return "SCC4"; 247 case FSL_CPM_TSA_SMC1: return "SMC1"; 248 case FSL_CPM_TSA_SMC2: return "SMC2"; 249 default: 250 break; 251 } 252 return NULL; 253 } 254 255 static u32 tsa_cell_id2csel(struct tsa *tsa, u32 cell_id) 256 { 257 switch (cell_id) { 258 case FSL_CPM_TSA_SCC2: return TSA_SIRAM_ENTRY_CSEL_SCC2; 259 case FSL_CPM_TSA_SCC3: return TSA_SIRAM_ENTRY_CSEL_SCC3; 260 case FSL_CPM_TSA_SCC4: return TSA_SIRAM_ENTRY_CSEL_SCC4; 261 case FSL_CPM_TSA_SMC1: return TSA_SIRAM_ENTRY_CSEL_SMC1; 262 case FSL_CPM_TSA_SMC2: return TSA_SIRAM_ENTRY_CSEL_SMC2; 263 default: 264 break; 265 } 266 return TSA_SIRAM_ENTRY_CSEL_NU; 267 } 268 269 static int tsa_add_entry(struct tsa *tsa, struct tsa_entries_area *area, 270 u32 count, u32 cell_id, u32 flags) 271 { 272 void *__iomem addr; 273 u32 left; 274 u32 val; 275 u32 cnt; 276 u32 nb; 277 278 addr = area->last_entry ? area->last_entry + 4 : area->entries_start; 279 280 nb = DIV_ROUND_UP(count, 8); 281 if ((addr + (nb * 4)) > area->entries_next) { 282 dev_err(tsa->dev, "si ram area full\n"); 283 return -ENOSPC; 284 } 285 286 if (area->last_entry) { 287 /* Clear last flag */
288 clrbits32(area->last_entry, TSA_SIRAM_ENTRY_LAST);
289 } 290 291 left = count; 292 while (left) { 293 val = TSA_SIRAM_ENTRY_BYTE | tsa_cell_id2csel(tsa, cell_id); 294 295 if (left > 16) { 296 cnt = 16; 297 } else { 298 cnt = left; 299 val |= TSA_SIRAM_ENTRY_LAST; 300 area->last_entry = addr; 301 } 302 val |= TSA_SIRAM_ENTRY_CNT(cnt - 1); 303 304 out_be32(addr, val); 305 addr += 4; 306 left -= cnt; 307 } 308 309 return 0; 310 } 311