8 Feb
2016
8 Feb
'16
5:43 p.m.
On Fri, Feb 05, 2016 at 12:19:07PM +0530, Vinod Koul wrote:
From: "Dharageswari.R" dharageswari.r@intel.com
The SoC has MCLK output which is typically required by codecs. The MCLK is controlled by DSP FW, so driver can configure that by sending DMA_CONTROL IPC. The configuration for MCLK is present in the endpoint blob.
For integration with CODEC drivers this clock should really be exposed via the clock API too.