On Wed, Sep 15, 2021 at 07:06:14PM +0200, Nicolas Frattaroli wrote:
On Mittwoch, 15. September 2021 16:10:12 CEST Mark Brown wrote:
Why is this not part of the normal bus format configuration? I don't know what this is but it sounds a lot like I2S mode...
This affects all TDM I2S modes, i.e. TDM Normal, TDM Left Justified and TDM Right Justified.
Without tdm-fsync-half-frame, we purportedly get the following output in TDM Normal Mode (I2S Format): (ch0l = channel 0 left, ch0r = channel 0 right)
fsync: _____________________________ ____________________________ sdi/sdo: ch0l, ch0r, ..., ch3l, ch3r, ch0l, ch0r, ...
With tdm-fsync-half-frame, we purportedly get the following:
fsync: _____________________________ ____________________________ sdi/sdo: ch0l, ch1l, ch2l, ch3l, ch0r, ch1r, ch2r, ch3r
At least, according to the TRM. I do not have an oscilloscope to verify this myself, and in the following paragraphs, I will elaborate why this seems confusing to me.
fsync-half-frame is just normal TDM for I2S, the default mode is how DSP mode normally operates. I don't know that there's any pressing need to support mix'n'match here, you could but it should be through the TDM configuration API.
So to answer the question, it's not part of the bus format because it applies to three bus formats, and I'm completely out of my depth here and wouldn't define three separate bus formats based on my own speculation of how this works.
It is part of the bus format really. I suspect the hardware is the kind that only really implements DSP mode and can just fake up a LRCLK for I2S in order to interoperate.