Re: [alsa-devel] [PATCH 1/5] ASoC: fsl_spdif: Use clk_set_rate() for spdif root clock only

On Wed, Apr 30, 2014 at 06:54:05PM +0800, Nicolin Chen wrote:

The clock mux for the Freescale S/PDIF controller has eight clock sources while most of them are from other moudles and even system clocks that do not allow a rate-changing operation.

Applied, thanks.