On Mon, Mar 04, 2013 at 06:25:05PM +0000, John Graham wrote:
You should CC maintainers on e-mails, often things just on the list get lost in the noise.
The problem now is that the I2S data lines don't look right - the line from codec to TX28 looks like a (more-or-less) square wave with the same period as the I2S clock, but only going from ~3.1 - ~3.5 V, as opposed to the 0 - ~3.3 V I expect. Furthermore, it's a pretty regular square wave - it doesn't have all the breaks you see on a working I2S data line.
My immediate thought here is that you're probably seeing some sort of electrical problem if the logic levels aren't being hit - normally this is because both ends of the link are driving simultaneously. I'd check the pin mux settings on the SoC, probably in arch/arm, to make sure that everything on the SoC is in the correct mode then check that the CPU is configured as a slave (which sounds like the intended configuration).