When j7200 SOM is attached to the CPB we only have parent clock for 48KHz family and the rate of the parent clock is 2359296000Hz.
Signed-off-by: Peter Ujfalusi peter.ujfalusi@ti.com --- sound/soc/ti/j721e-evm.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/sound/soc/ti/j721e-evm.c b/sound/soc/ti/j721e-evm.c index cb074af47a7d..29b73303f3fc 100644 --- a/sound/soc/ti/j721e-evm.c +++ b/sound/soc/ti/j721e-evm.c @@ -525,6 +525,14 @@ static const struct j721e_audio_match_data j721e_cpb_ivi_data = { }, };
+static const struct j721e_audio_match_data j7200_cpb_data = { + .board_type = J721E_BOARD_CPB, + .num_links = 2, /* CPB pcm3168a */ + .pll_rates = { + [J721E_CLK_PARENT_48000] = 2359296000u, /* PLL4 */ + }, +}; + static const struct of_device_id j721e_audio_of_match[] = { { .compatible = "ti,j721e-cpb-audio", @@ -532,6 +540,9 @@ static const struct of_device_id j721e_audio_of_match[] = { }, { .compatible = "ti,j721e-cpb-ivi-audio", .data = &j721e_cpb_ivi_data, + }, { + .compatible = "ti,j7200-cpb-audio", + .data = &j7200_cpb_data, }, { }, };