5 Oct
2020
5 Oct
'20
1:31 p.m.
On Wed, Sep 30, 2020 at 09:11:36PM -0500, Samuel Holland wrote:
The codec supports only power-of-two BCLK/LRCK divisors. If either the slot width or the number of slots is not a power of two, the LRCK divisor must be rounded up to provide enough space. To do that, use order_base_2 (instead of ilog2, which rounds down).
Since the rounded divisor is also needed for setting the SYSCLK/BCLK divisor, return the order base 2 instead of fully calculating the hardware register encoding.
Signed-off-by: Samuel Holland samuel@sholland.org
Acked-by: Maxime Ripard mripard@kernel.org
Maxime