3 Mar
2022
3 Mar
'22
9:50 p.m.
Quoting Srinivasa Rao Mandadapu (2022-03-03 06:30:51)
Update description for audio clock reset control property, which is required for latest chipsets, to allow rx, tx and wsa bus clock enabling in software control mode by configuring dynamic clock gating control registers.
Signed-off-by: Srinivasa Rao Mandadapu quic_srivasam@quicinc.com Co-developed-by: Venkata Prasad Potturu quic_potturu@quicinc.com Signed-off-by: Venkata Prasad Potturu quic_potturu@quicinc.com Acked-by: Rob Herring robh@kernel.org
Reviewed-by: Stephen Boyd swboyd@chromium.org