Le mer., juil. 6 2022 at 22:13:28 +0100, Aidan MacDonald aidanmacdonald.0x0@gmail.com a écrit :
On some Ingenic SoCs, such as the X1000, there is a programmable divider used to generate the I2S system clock from a PLL, rather than a fixed PLL/2 clock. It doesn't make much sense to call the clock "pll half" on those SoCs, so the clock name should really be a SoC-dependent value.
Do you really need the .set_sysclk() callback? I've never seen it used on any of the Ingenic boards I have, so to me it's pretty much dead code. Unless you do use this callback, I'd suggest to drop this patch until you do need it.
Cheers, -Paul
Signed-off-by: Aidan MacDonald aidanmacdonald.0x0@gmail.com
sound/soc/jz4740/jz4740-i2s.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 3a21ee9d34d1..80b355d715ce 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -71,6 +71,8 @@ struct i2s_soc_info { struct reg_field field_tx_fifo_thresh; struct reg_field field_i2sdiv_capture; struct reg_field field_i2sdiv_playback;
- const char *pll_clk_name;
};
struct jz4740_i2s { @@ -265,7 +267,7 @@ static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, clk_set_parent(i2s->clk_i2s, parent); break; case JZ4740_I2S_CLKSRC_PLL:
parent = clk_get(NULL, "pll half");
parent = clk_get(NULL, i2s->soc_info->pll_clk_name);@@ -387,6 +389,7 @@ static const struct i2s_soc_info jz4740_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
- .pll_clk_name = "pll half",
};
static const struct i2s_soc_info jz4760_i2s_soc_info = { @@ -395,6 +398,7 @@ static const struct i2s_soc_info jz4760_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
- .pll_clk_name = "pll half",
};
static struct snd_soc_dai_driver jz4770_i2s_dai = { @@ -421,6 +425,7 @@ static const struct i2s_soc_info jz4770_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
- .pll_clk_name = "pll half",
};
static const struct i2s_soc_info jz4780_i2s_soc_info = { @@ -429,6 +434,7 @@ static const struct i2s_soc_info jz4780_i2s_soc_info = { .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
- .pll_clk_name = "pll half",
};
static const struct snd_soc_component_driver jz4740_i2s_component = {
2.35.1